UVM (Universal Verification Methodology) is a SystemVerilog language based Verification methodology which is getting more and more popularity and adoption in the VLSI Verification industry.

UVM consists of a defined methodology for architecting modular testbenches for design verification. UVM has a library of classes that helps in designing and implementing modular testbench components and stimulus. The Universal Verification Methodology is a collection of API and proven verification guidelines written for SystemVerilog that help an engineer to create an efficient verification environment.

SVM/UVM Module:

  • Introduction to Universal Verification Methodology.
  • UVM Test Bench Architecture.
  • UVM Base Class Hierarchy.
  • UVM Factory.
  • Stimulus Modelling.
  • Test Bench Overview.
  • UVM Phases & Reporting Mechanisms.
  • Creating UVM Test-Bench Components.
  • UVM Callbacks and Events.
  • UVM – RAL.
  • Final Project.
  • Classroom Course:      INR 65000 (GST Excluded)
  • Online Course:             INR 55000 (GST Excluded)
  • Batch Size:                  15-20
  • Placement:                  100% Placement Assistance
  • Trainer:                        10+ Years of Industrial Experience      
  • Duration:                                  4 Months
  • New Batchistration Starts:       11 June 2020
  • Registration Starts:                   21 June 2020

Week Plan

  • Weekend Batch – 9:00 A.M to 6:00 P.M
  • Weekday Batch – 10:00 A.M to 5:00 P.M