RTL is based on synchronous logic and contains three primary pieces namely, registers which hold state information, combinatorial logic which defines the nest state inputs and clocks that control when the state changes.

The RTL design is captured using a hardware description language (HDL) such as Verilog or VHDL. While these languages are capable of defining systems at other levels of abstraction, it is generally the RTL semantics of these languages, and indeed a subset of these languages defined as the synthesizable subset. This means the language constructs that can be reliably fed into a logic synthesis tool which in turn creates the gate-level abstraction of the design that is used for all downstream implementation operations.

RTL Design Module:

  • VLSI Design Flow.
  • Fundamentals of Digital Design.
  • Basics of Linux.
  • Scripting- TCL/PERL.
  • Basics of Verilog and System Verilog.
  • RTL Integration
  • Power Aware Design Techniques.
  • RTL Synthesis.
  • Logic Equivalence Checks.
  • Final Project.
  • Classroom Course:      INR 85000 (GST Excluded)
  • Online Course:             INR 75000 (GST Excluded)
  • Batch Size:                  15-20
  • Placement:                  100% Placement Assistance
  • Trainer:                        10+ Years of Industrial Experience
  • Duration:                       4-5 Months
  • New Batch:                   3 July 2020
  • Registration Starts:       21 June 2020

Week Plan:

  • Weekend Batch – 9:00 A.M to 6:00 P.M
  • Weekday Batch – 10:00 A.M to 5:00 P.M