Design verification is an essential step in the development of any product and can also be referred as qualification testing. Design verification ensures that the product as designed is the same as the product as intended. 

Design Verification consist of:

  • Logic Simulation and Circuit Simulation in which detailed functionality and timing of the design are checked by means of simulation.
  • Functional Verification, in which functional models describing the functionality of the design are developed to check against the behavioural specification of the design without detailed timing simulation.
  • Formal Verification in which the functionality is checked against a “golden” model. Formal verification further includes property checking (or model checking), in which the property of the design is checked against some presumed “properties and equivalence checking, in which the functionality is checked against a “golden” model.

Design & Verification Module:

  • Introduction to ASIC Flow.
  • Understanding Digital Design Concepts.
  • Fundamentals of Verilog and System Verilog.
  • Fundamentals of Verification.
  • Verification IP Development.
  • RTL Debugging.
  • Functional Verification.
  • SOC Design & Verification.
  • Basics of Linux, PERL Scripting./li>
  • Final Project.
  • Classroom Course:      INR 75000 (GST Excluded)
  • Online Course:             INR 60000 (GST Excluded)
  • Batch Size:                  15-20
  • Placement:                  100% Placement Assistance
  • Trainer:                        12+ Years of Industrial Experience
  • Duration:                       5-6 Months
  • New Batch:                   1 July 2020
  • Registration Starts:       20 June 2020

Week Plan:

  • Weekend Batch – 9:00 A.M to 6:00 P.M
  • Weekday Batch – 10:00 A.M to 5:00 P.M