Physical verification is a process whereby an integrated circuit layout (IC layout) design is verified via EDA software tools to ensure correct electrical and logical functionality and manufacturability. Physical Verification Engineer will do a list of checks before the chip is sent for fabrication.

Physical Verification Module:
It consists of following number of checks:

  • LVS
  • DRC
  • ERC
  • Density Checks
  • Reliability Checks
  • Classroom Course:     INR 55000 (GST Excluded)
  • Online Course:             INR 45000 (GST Excluded)
  • Batch Size:                   15-20
  • Placement:                   100% Placement Assistance
  • Trainer:                         13+ Years of Industrial Experience  
  • Duration:                       1-2 Months
  • New Batch:                   23 May 2020
  • Registration Starts:     13 May 2020

Week Plan

  • Weekend Batch – 9:00 A.M to 6:00 P.M
  • Weekday Batch – 10:00 A.M to 5:00 P.M